1. Field of the Invention
The invention generally relates to a variable gain amplifier and, more particularly, to a variable gain amplifier suitable for use in a semiconductor integrated circuit for communications.
2. Discussion of Background
A conventional variable gain amplifier may employ a variable gain amplifier, shown in FIG. 2A and FIG. 2B, as a configuration block. For more detail see non-patent document 1 below. The variable gain amplifier controls a gain with bias current by taking advantage of the gain of a transistor being proportional to the bias current.
FIG. 2A and FIG. 2B show a conventional variable gain amplifier 200. FIG. 2A is a block circuit diagram of the variable gain amplifier 200 comprising variable gain unit amplifiers (hereinafter referred to merely as unit amplifiers) that are series connected in three stages, and FIG. 2B is a circuit diagram of the unit amplifier making up the respective stages.
Since there is a limitation to a variable gain range of the variable gain amplifier with a unit amplifier (VGA) 202 only in one stage as shown in FIG. 2A, the variable gain amplifier is generally configured such that the unit amplifiers in a plurality of stages (in the case of an example shown in FIG. 2A, 3 stages from VGA1 to VGA3) are connected in series so as to obtain a large variable gain range. The respective unit amplifiers 202 are made up of a variable gain differential amplifier 204 as shown in FIG. 2B, comprising differential pair transistors wherein respective emitters of transistors Q1, Q2 are connected with each other, and respective bases of the transistors Q1, Q2 serve as input terminals, and a variable current source 205 for supplying bias current to the differential pair transistors. Control of a gain of the variable gain differential amplifier 204 is implemented by controlling a current value of the variable current source 205.
In FIG. 2A, reference numeral C denotes a capacitor for cutting direct current (DC), IN an input signal to the variable gain amplifier 200, and OUT an output signal. Further, FIG. 2B IN denotes an input signal to the variable gain differential amplifier 204, OUT an output signal, Vcc a power source voltage for the variable gain differential amplifier, and Vbias a bias power source voltage for supplying bias current to the respective bases of the differential pair transistors Q1, Q2 via respective resistors R1, R2. Resistors RL1, RL2 are load resistors of the differential pair transistors Q1, Q2, respectively.
[Non-patent Document 1]
Yamawaki et al., “A 2.7-V GSM RF TRANCEIVER IC” in IEEE Journal of solid Sate Circuits, Vol. 32, No. 12, December, 1997
[Non-patent Document 2]
Kenington, Peter B., “High Linearity RF Amplifier Design”, Artech House, Inc., 1979, pp. 161-163
With the conventional circuit shown in FIG. 2, there occurs amplitude distortion when a large signal is inputted thereto due to non-linearity of the respective variable gain differential amplifiers making up the variable gain amplifier, to which a good deal of thought has not been given. Accordingly, it has not been possible to obtain a variable gain amplifier capable of satisfying a requirement for low distortion-and low noise even at times of a large input signal.